Verification remains the most time-consuming part of the chip design process. EDA vendors are already adopting LLMs to assist with various tasks, including code generation for different UVM testbench components. Currently, a large quantity of third-party LLMs is available, combined with numerous techniques that can be used for generating UVM testbench components. The trend is to combine them into a multi-agent solution to maximize performance. However, there is no comprehensive study that evaluates which models and techniques are the most suitable for the task. To find the most optimal method of generating a UVM testbench resulting in the highest accuracy, we propose to create an evaluation framework that would test a combination of various LLMs and techniques. The collaboration is planned as follows. After the incoming students are on-site NCKU EE, we will have regular meetings to do face-to-face technical discussions. The preferred time of stay is 3-6 months. We would propose the following rough timeline: 1) Current state of research and trends (~4 weeks). 2) Dataset preparation (~4 weeks). 3) Experiments (~8 weeks). 4) Results analysis (~4 weeks). 5) Research paper outline (~4 weeks). This financial aid will include the students' scholarship and air ticket subsidy.